Method for controlling die attach fillet height to reduce die shear stress

ABSTRACT

A method and an apparatus for preventing cracking and delamination in a packaged semiconductor chip by controlling the die attach fillet height. Specifically, the present invention controls the die attach material height, thereby controlling the die attach fillet height, and thereby reducing shear stress in the die itself. Advantages of the present invention include increasing wire-bond reliability and package reliability without the need for requalification of existing products. By using currently qualified molding compounds and die attach epoxies in conjunction with the present technique for controlling the die attach epoxy height in order to control the die attach fillet height, the overall assembly process may be maintained. Thus, neither thermal performance nor electrical performance is compromised.

FIELD OF THE INVENTION

[0001] The present invention relates to the assembly and packaging ofsemiconductor chips. More particularly, the present invention relates toassembly and packaging of wire-bonded dies in semiconductor chips. Evenmore particularly, the present invention relates to reducing shearstress in the dies of semiconductor chips.

BACKGROUND OF THE INVENTION

[0002] Currently, the semiconductor industry is demanding better dieattach, better packaging, better wire-bonding, and the like, to improveproduct reliability. Each die is generally attached into a die attacharea of a semiconductor package using a eutectic material layer, such asa gold-silicon (Au—Si) eutectic layer and a silver-silicon (Ag—Si), oran organic die attach material, such as an epoxy or a polyimide. Distalends of a wire are generally respectively bonded to a die and to a lead.A chip is generally secured well into the package; and the dieattachment area may provide electric coupling between the chip and theremainder of the lead system. A major requirement for the die attachmentarea is that it be extremely flat to intimately retain the chip in thepackage.

[0003] With respect to die attachment, the basic objective is to providethe best adhesion between the chip and the package as is possible and toprovide the best electrically and/or thermally conducting path or eventhe best insulating material therebetween, depending on the specificchip application. As such, the die attachment should be strong toprevent delamination during subsequent processing steps or during use.The most widely used die attach materials include gold-filled (Au) andsilver-filled (Ag) polyimides and epoxies for electrical and thermalconduction. For insulation purposes, silica-loaded polymers may be usedas a die attach material. Unfortunately, both insulator-filled andconductor-filled related art die attach materials tend to delaminate andcrack due to their inherent internal stresses after curing. Further,most molding compounds tend to flex around the die during temperaturecycling, also inducing cracking or propagating pre-existing cracks.

[0004] The related art has attempted to address these issues byproviding lower stress molding compounds and lower stress die attachepoxies. However, the use of lower stress molding compounds wouldrequire requalification of many existing products. Such productconversions are both difficult and exorbitant. In addition, using alower stress molding compound requires a decreased loading of silica(SiO₂) particles which, then, compromises thermal performance.Similarly, using a lower stress die attach epoxy requires a decreasedloading of Au or Ag particles, compromising not only thermal performancebut also electrical performance.

[0005] Another related art approach has been to use a very low epoxyfillet height in the range of less than 33.33% (i.e., <5 mils filletheight for a 15-mil thick die) for reducing any thermally-induced stressonly at the die/encapsulant interface, wherein the encapsulantspecifically comprises a glob-top material. Typically, a glob-topencapsulant is known to have inherent weaknesses at the die/glob-topinterface, because it is dispensed from a dispenser under ambientconditions over and onto the die's upper surface. As such, the glob-topencapsulant tends to be riddled with voids, compromising adhesion, andtherefore, contributing to delamination. However, this related artapproach does not address the problem of shear stress in the fillet, inthe cracking of a thicker die, nor between the metal circuitry and thebulk silicon on the die. Likewise, these related art techniques do notaddress problems related to packaging materials other than thoseassociated with the glob-top variety. Therefore, a long-felt need isseen to exist for a method and an apparatus for controlling the dieattachment process in order to prevent cracking as well as delaminationin a semiconductor chip package under many processing and useconditions.

BRIEF SUMMARY OF THE INVENTION

[0006] Accordingly, the present invention provides a method and anapparatus for preventing cracking and delamination in a semiconductorchip package, especially a “plastic” package, such as a plastic quadflat package (PQFP), a thin quad flat package (TQFP), a plastic leadlesschip carrier (PLCC) package, a small outline integrated circuit (SOIC)package, although less problematic, some undesirable shear stress maystill exist), and any other standard or nonstandard plastic package.Particularly, a ball grid array (BGA) package with an over-moldedcompound (or “molding compound”), which also experiences cracking anddelamination during thermal cycling, thermal shock, or normal operation.

[0007] The present invention solves these plastic packaging problems bycontrolling the die attach fillet height, thereby reducing shear stressin the die itself The molding compound, such as is used with a BGA, maybe applied by dispensing it through gate in a transfer mold (e.g., RTM:resin transfer molding). After filling the mold with the moldingcompound, heat and pressure may be applied for curing, densifying, anddevoiding the molding compound. This technique, when used in the presentmethod for controlling fillet height, results in a non-delaminatingsemiconductor package, especially for a BGA.

[0008] By example only, the present invention empirical data correspondsto various fillet heights that are proportional to various diethicknesses in a range of approximately 4 mils to 30 mils contained in aBGA package under experimental conditions, such as thermal cycling andthermal shock. By using a fillet height in a preferred range of greaterthan approximately 33% to approximately 75% of the die thickness, thepresent invention circumvents both (1) the related art problem ofcoefficient of thermal expansion (CTE) mismatch among the elementswithin a packaged device, which would otherwise occur in the related artfillet height range of <33% of the die thickness, thereby leading tovoids in the die attach material, cracking thereof, and poor thermalconductivity; and (2) the related art problem of high shearstress-induced failures, such as shear stress-induced cracking in thedie attach material as well as the die itself, which would otherwiseoccur in the related art fillet height range of >75% of the diethickness. Surprisingly, the present invention experimental reliabilitydata demonstrates that a nominal fillet height of approximately 50% ofthe die thickness induces the lowest shear stress in a thicker silicondie (e.g., in a range of approximately 8 mils to approximately 14 mils,preferably in a range of approximately 10 mils to approximately 14mils). Also surprisingly, a thinner die having a thickness in a range ofless than 8 mils, actually imparts adverse results in contravention tothe semiconductor packaging industry's belief. A die attachpick-and-place machine, such as an ESEC 2007™ may be used in the presentinvention. More specifically, the present invention provides a methodand an apparatus controlling the die attach epoxy height, therebycontrolling the die attach fillet height, and thereby reducing shearstress in the die itself.

[0009] Advantages of the present invention include increasing wire-bondreliability and package reliability without the need for requalificationof existing products. By using currently qualified molding compounds anddie attach epoxies in conjunction with the present technique forcontrolling the die attach epoxy height in order to control the dieattach fillet height, the overall assembly process may be maintained.Thus, the present invention also has the advantage of compromisingneither thermal performance nor electrical performance. Also, bycontrolling the fillet height by regulating the amount of die attachmaterial to be applied, less die attach material is consumed in thepackaging process. As such, the present invention method and apparatusprevent cracking and delamination in a semiconductor chip package,especially a ball grid array (BGA) package, during thermal cycling,thermal shock, and normal use, thereby resulting in a more robustpackage.

BRIEF DESCRIPTION OF THE DRAWING(S)

[0010] For a better understanding of the present invention, reference ismade to the below-referenced accompanying drawings. Reference numbersrefer to the same or equivalent parts of the present inventionthroughout the several figures of the drawings.

[0011]FIG. 1 is a plan-view of a die attached to a semiconductor chippackage in a die attachment area with a standard die attach fillet, inaccordance with a preferred embodiment of the present invention.

[0012]FIG. 2 is a cross-sectional view of the features as shown in FIG.1, further showing a die attach material forming a standard die attachfillet having a height of approximately 50% of the die thickness, inaccordance with a preferred embodiment of the present invention.

[0013]FIG. 3 is a cross-sectional side view of the features as shown inFIG. 1, further showing a die attach material forming a standard dieattach fillet having a height of approximately 50% of the die thickness,in accordance with a preferred embodiment of the present invention.

[0014]FIG. 4 is an opposing cross-sectional side view of the features asshown in FIG. 1, further showing a die attach material forming astandard die attach fillet having a height of approximately 50% of thedie thickness, in accordance with a preferred embodiment of the presentinvention.

[0015]FIG. 5 is a plan-view of a die attached to a semiconductor chippackage in a die attachment area with a high/even die attach fillet, inaccordance with the related art.

[0016]FIG. 6 is a cross-sectional view of the features as shown in FIG.5, further showing a die attach material forming a high/even die attachfillet having a height of approximately 90% of the die thickness, inaccordance with the related art.

[0017]FIG. 7 is a cross-sectional side view of the features as shown inFIG. 5, further showing a die attach material forming a high/even dieattach fillet having a height of approximately 90% of the die thickness,in accordance with the related art.

[0018]FIG. 8 is an opposing cross-sectional side view of the features asshown in FIG. 5, further showing a die attach material forming ahigh/even die attach fillet having a height of approximately 90% of thedie thickness, in accordance with the related art.

[0019]FIG. 9 is a plan-view of a die attached to a semiconductor chippackage in a die attachment area with a high/low die attach fillet, inaccordance with the related art.

[0020]FIG. 10 is a cross-sectional view of the features as shown in FIG.9, further showing a die attach material forming a high/low die attachfillet, a high side of the die attach fillet having a height ofapproximately 90% of the die thickness and a low side of the die attachfillet having a height of approximately 25% of the die thickness, inaccordance with the related art.

[0021]FIG. 11 is a cross-sectional side view of the features as shown inFIG. 9, further showing a die attach material forming a high/low dieattach fillet, the high side of the die attach fillet having a height ofapproximately 90% of the die thickness, in accordance with the relatedart.

[0022]FIG. 12 is an cross-sectional opposing side view of the featuresas shown in FIG. 9, further showing a die attach material forming ahigh/low die attach fillet, the low side of the die attach fillet havinga height of approximately 25% of the die thickness, in accordance withthe related art.

[0023]FIG. 13 is a partial cross-sectional view a die attached to asemiconductor chip package base in a die attachment area with a dieattach fillet, showing the critical dimensional relationship between thedie attach fillet height Z=B−A and the die thickness B, wherein A=theportion of the die thickness B not covered by the fillet, in accordancewith the present invention.

[0024]FIG. 14 is a partial cross-sectional view of a die attached to aBGA semiconductor chip package in a die attachment area with a dieattach fillet, showing the critical structural relationship between thedie attach fillet and the die, in accordance with the present invention.

[0025]FIG. 15 is a partial cross-sectional view, a die attached to asemiconductor chip package base, such as a BGA package, in a dieattachment area with a die attach fillet, showing the criticalstructural relationship (i.e., the fillet height being approximately 50%of the die thickness) between the die attach fillet and the die, furtherhaving a molding compound disposed on the die, on the fillet, on aportion of the die attach material, and on a portion of the packagebase, in accordance with the present invention.

[0026]FIG. 16 is a cross-sectional view of a die having a die attachfillet, showing the preferred structural relationship (i.e., the filletheight being in a range of approximately 0% to approximately 75% of thedie thickness along an approximately central 50% of the die width of anygiven side of the die), in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0027] FIGS. 5-12 illustrate the problematic features of the related artsemiconductor packages which are discussed, infra, in relation with theproblems solved by the present invention, as illustrated in FIGS. 14 and12-15.

[0028]FIG. 1 illustrates, in plan-view, a die 5 attached to asemiconductor chip package base 10 in a die attachment area with astandard die attach fillet (not shown), in accordance with a preferredembodiment of the present invention.

[0029]FIG. 2 illustrates, in cross-sectional view, the features as shownin FIG. 1, further showing a die attach material 20 forming a standarddie attach fillet 30 having a height of approximately 50% of the die 5thickness, wherein the standard die attach fillet height comprises anapproximately uniform height distribution around the die 5, inaccordance with a preferred embodiment of the present invention.

[0030]FIG. 3 illustrates, in cross-sectional side view, the features asshown in FIG. 1, further showing a die attach material 20 forming astandard die attach fillet 30 having a height of approximately 50% ofthe die 5 thickness, wherein the standard die attach fillet heightcomprises an approximately uniform height distribution around the die 5,in accordance with a preferred embodiment of the present invention.

[0031]FIG. 4 illustrates, in opposing cross-sectional side view, thefeatures as shown in FIG. 1, further showing a die attach material 20forming a standard die attach fillet 30 having a height of approximately50% of the die 5 thickness, wherein the standard die attach filletheight comprises an approximately uniform height distribution around thedie 5, in accordance with a preferred embodiment of the presentinvention.

[0032]FIG. 5 illustrates, in plan-view, a die 5 attached to asemiconductor chip package base 10 in a die attachment area with ahigh/even die attach fillet (not shown), in accordance with the relatedart.

[0033]FIG. 6 illustrates, in cross-sectional view, the features as shownin FIG. 5, further showing a die attach material 20 forming a high/evendie attach fillet 30 having a height of approximately 90% of the die 5thickness, wherein the high/even die attach fillet height comprises anapproximately uniform height distribution around the die 5, inaccordance with the related art.

[0034]FIG. 7 illustrates, in cross-sectional side view, the features asshown in FIG. 5, further showing a die attach material 20 forming ahigh/even die attach fillet 30 having a height of approximately 90% ofthe die 5 thickness, wherein the high/even die attach fillet heightcomprises an approximately uniform height distribution around the die 5,in accordance with the related art.

[0035]FIG. 8 illustrates, in opposing cross-sectional side view, thefeatures as shown in FIG. 5, further showing a die attach material 20forming a high/even die attach fillet 30 having a height ofapproximately 90% of the die 5 thickness, wherein the high/even dieattach fillet height comprises an approximately uniform heightdistribution around the die 5, in accordance with the related art.

[0036]FIG. 9 illustrates, in plan-view, a die 5 attached to asemiconductor chip package base 10 in a die attachment area with ahigh/low die attach fillet (not shown), in accordance with the relatedart.

[0037]FIG. 10 illustrates, in cross-sectional view, the features asshown in FIG. 9, further showing a die attach material 20 forming ahigh/low die attach fillet 30, a high side of the die attach fillet 30having a height of approximately 90% of the die 5 thickness and a lowside of the die attach fillet 30 having a height of approximately 25% ofthe die 5 thickness, wherein the high/low die attach fillet heightcomprises a non-uniform height distribution around the die 5, inaccordance with the related art.

[0038]FIG. 11 illustrates, in cross-sectional side view, the features asshown in FIG. 9, further showing a die attach material 20 forming ahigh/low die attach fillet 30, a high side of the die attach fillet 30having a height of approximately 90% of the die 5 thickness and a lowside of the die attach fillet 30 having a height of approximately 25% ofthe die 5 thickness, wherein the high/low die attach fillet heightcomprises a non-uniform height distribution around the die 5, inaccordance with the related art.

[0039]FIG. 12 illustrates, in cross-sectional opposing side view, thefeatures as shown in FIG. 9, further showing a die attach material 20forming a high/low die attach fillet 30, a high side of the die attachfillet 30 having a height of approximately 90% of the die 5 thicknessand a low side of the die attach fillet 30 having a height ofapproximately 25% of the die 5 thickness, wherein the high/low dieattach fillet height comprises a non-uniform height distribution aroundthe die 5, in accordance with the related art.

[0040]FIG. 13 illustrates, in partial cross-sectional view, a die 5attached to a semiconductor chip package base 10 in a die attachmentarea with a die attach fillet 30, showing the critical dimensionalrelationship between the die attach fillet height Z=B−A and the diethickness B, wherein A=the portion of the die thickness B not covered bythe fillet 30, in accordance with the present invention.

[0041]FIG. 14 illustrates, in partial cross-sectional view, a die 5attached to a semiconductor chip package base 10, such as a BGA package,in a die attachment area with a die attach fillet 30, showing thecritical structural relationship (i.e., the fillet height beingapproximately 50% of the die thickness) between the die attach fillet 30and the die 5, in accordance with the present invention.

[0042]FIG. 15 illustrates, in partial cross-sectional view, a die 5attached to a semiconductor chip package base 10, such as a BGA package,in a die attachment area with a die attach fillet 30, showing thecritical structural relationship (i.e., the fillet height beingapproximately 50% of the die thickness) between the die attach fillet 30and the die 5, further having a molding compound 60 disposed on the die5, on the fillet 30, on a portion of the die attach material 20, and ona portion of the package base 10, in accordance with the presentinvention.

[0043]FIG. 16 illustrates, in cross-sectional view, a die 5 having a dieattach fillet 30, showing the critical structural relationship (i.e.,the fillet height Z=B−A being in a range of approximately 0% toapproximately 75% of the die thickness Y=B along an approximatelycentral 50% of the die width X of any given side of the die 5), inaccordance with the preferred embodiment present invention. In essence,Z≅(0% to 75%)Y≅(0% to 75%)B is the constraint for a locationapproximately ≧25% X (i.e., at least 25% inboard from each edge 6 on anygiven side of the die 5). Preferably, Z≅(>33% to 75%)Y≅(>33% to 75%)B isthe constraint for a location approximately ≧25% X (i.e., at least 25%inboard from each edge 6 on any given side of the die 5). Thisconstraint for the preferred embodiment is surprisingly effective inreducing overall shear stress in the packaged device. During theassembly process, controlling the fillet height in the outboard regions(i.e., less than 25% X) is very difficult. Thus, the present methodconstrains the fillet height in the inboard region (i.e., at least 25%inboard from each edge 6 on any given side of the die 5) where thepotential damage suffered from shear stress would otherwise be at itsgreatest. In so doing, the present method results in a packaged devicehaving significantly reduced shear stress.

[0044] The present invention method of reducing shear stress in apackaged semiconductor chip, generally comprises the steps of: providinga semiconductor chip package base 10 having a semiconductor chipdisposed therein and having a die attachment area; providing a die 5having a thickness Y, a width X, and at least one side; providing a dieattach material 20; controlling an amount of the die attach material 20disposed between the die 5 and the semiconductor chip package base 10,whereby at least one portion of the die attach material 20 forms atleast one meniscus on the at least one side of the die 5, whereby the atleast one meniscus forms at least one die attach fillet 30 upon curingof the die attach material 20, thereby controlling at least one heightZ=B−A of the at least one die attach fillet 30, and thereby reducingshear stress in the die 5; and completing packaging of the semiconductorchip.

[0045] The present invention reduced shear stress packaged semiconductorchip, generally comprises: a semiconductor chip package base 10 having asemiconductor chip disposed therein and having a die attachment area; adie 5 having at least one side; a controlled amount of die attachmaterial 20 disposed between the die 5 and the semiconductor chippackage base 10; at least one portion of the die attach material 20forming at least one meniscus on the at least one side of the die 5, theat least one meniscus forming at least one die attach fillet 30 uponcuring of the die attach material 20, the at least one die attach fillet30 having at least one controlled height Z=B—A, and the die 5 havingreduced shear stress.

[0046] In the present method and apparatus for reducing shear stress ina packaged semiconductor chip, the die 5 may comprise silicon and have athickness in a range of approximately 4 mils to approximately 30 mils,preferably approximately 10 mils to approximately 14 mils, as a somewhatthicker die has surprisingly superior crack resistance. A die 5, whichis sawn by step-cut, is preferable as having less pre-existing internalstresses and may preferably be approximately 367 mils² in plan area. Thedie attach material 20 may comprise an epoxy, and may comprise a fillerselected from a group consisting essentially of a conductor and aninsulator.

[0047] The die attach fillet height (i.e., “fillet percentage”) iscalculated by the simple relationship, fillet %=100(B−A)/B, whereinB=the die thickness, and wherein A=vertical distance of a die side whichhas not been coated with the die attach material. The die attach fillet30 may also comprise a standard height Z in a range of approximately 40%to approximately 60% (nominally approximately 50%) of the die thicknessY=B. By purposefully constraining the die attach fillet height toapproximately 50% of the die thickness, the present invention alsoreduces shear stress in the die which, in turn, reduces overall stressin the packaged semiconductor chip. The preferred embodiment (i.e.,greater than approximately 33%—approximately 75% of the die thicknesshas been discussed, supra, with respect to FIG. 16.

[0048] Information as herein shown and described in detail is fullycapable of attaining the above-described object of the invention, thepresently preferred embodiment of the invention, and is, thus,representative of the subject matter which is broadly contemplated bythe present invention. The scope of the present invention fullyencompasses other embodiments which may become obvious to those skilledin the art, and is to be limited, accordingly, by nothing other than theappended claims, wherein reference to an element in the singular is notintended to mean “one and only one” unless explicitly so stated, butrather “one or more.” All structural and functional equivalents to theelements of the above-described preferred embodiment and additionalembodiments that are known to those of ordinary skill in the art arehereby expressly incorporated by reference and are intended to beencompassed by the present claims.

[0049] Moreover, no requirement exists for a device or method to addresseach and every problem sought to be resolved by the present invention,for such to be encompassed by the present claims. Furthermore, noelement, component, or method step in the present disclosure is intendedto be dedicated to the public regardless of whether the element,component, or method step is explicitly recited in the claims. However,it should be readily apparent to those of ordinary skill in the art thatvarious changes and modifications in form, semiconductor material, andfabrication material detail may be made without departing from thespirit and scope of the inventions as set forth in the appended claims.No claim herein is to be construed under the provisions of 35 U.S.C. §112, sixth paragraph, unless the element is expressly recited using thephrase “means for.”

What is claimed:
 1. A method of reducing shear stress in a packagedsemiconductor chip, comprising the steps of: providing a semiconductorchip package base having a semiconductor chip disposed therein andhaving a die attachment area; providing a die having at least one side,said die comprising a semiconductor material selected from a groupconsisting essentially of silicon (Si), germanium (Ge), and galliumarsenide (GaAs), and each said at least one side having a thickness anda width; providing a die attach material; controlling an amount of saiddie attach material disposed between said die and said semiconductorchip package base, whereby at least one portion of said die attachmaterial forms at least one meniscus on said at least one side of thedie, whereby said at least one meniscus forms at least one die attachfillet upon curing of said die attach material, thereby controlling atleast one height of said at least one die attach fillet, and therebyreducing shear stress in said die; and completing packaging of saidsemiconductor chip.
 2. A method, as recited in claim 1, wherein said diecomprises a thickness in a range of approximately 4 mils toapproximately 30 mils.
 3. A method, as recited in claim 1, wherein saiddie attach material comprises an epoxy.
 4. A method, as recited in claim1, wherein said at least one die attach fillet comprises a standardheight in a range of approximately 0% to approximately 75% of said diethickness.
 5. A method, as recited in claim 4, wherein saidsemiconductor chip package base comprises a ball grid array (BGA).
 6. Amethod, as recited in claim 1, wherein said at least one die attachfillet comprises a standard height in a range of greater thanapproximately 33% to approximately 75% of said die thickness.
 7. Amethod, as recited in claim 6, wherein said standard height isconstrained in said range of greater than approximately 33% toapproximately 75% of said die thickness along an approximately central50% of said die width.
 8. A method, as recited in claim 1, wherein saidcompleting step comprises providing a molding compound disposed on saiddie, on said fillet, on at least one portion of said die attachmaterial, and on at least one portion of said package base.
 9. A method,as recited in claim 8, wherein said semiconductor chip package basecomprises a ball grid array (BGA).
 10. A method, as recited in claim 1,wherein said semiconductor chip package base comprises a ball grid array(BGA).
 11. A reduced shear stress packaged semiconductor chip,comprising: a semiconductor chip package base having a semiconductorchip disposed therein and having a die attachment area; a die having atleast one side, said die comprising a semiconductor material selectedfrom a group consisting essentially of silicon (Si), germanium (Ge), andgallium arsenide (GaAs), and each said at least one side having athickness and a width; and a controlled amount of die attach materialdisposed between said die and said semiconductor chip package base; atleast one portion of said die attach material forming at least onemeniscus on said at least one side of said die, said at least onemeniscus forming at least one die attach fillet upon curing of said dieattach material, said at least one die attach fillet having at least onecontrolled height, and said die having reduced shear stress.
 12. Apackaged semiconductor chip, as recited in claim 11, wherein said diecomprises a thickness in a range of approximately 4 mils toapproximately 30 mils.
 13. A packaged semiconductor chip, as recited inclaim 11, wherein said die attach material comprises an epoxy.
 14. Apackaged semiconductor chip, as recited in claim 11, wherein said atleast one die attach fillet comprises a standard height in a range ofapproximately 0% to approximately 75% of said die thickness.
 15. Apackaged semiconductor chip, as recited in claim 14, wherein saidsemiconductor chip package base comprises a ball grid array (BGA).
 16. Apackaged semiconductor chip, as recited in claim 11, wherein said atleast one die attach fillet comprises a standard height in a range ofgreater than approximately 33% to approximately 75% of said diethickness.
 17. A packaged semiconductor chip, as recited in claim 16,wherein said standard height is constrained in said range of greaterthan approximately 33% to approximately 75% of said die thickness alongan approximately central 50% of said die width.
 18. A packagedsemiconductor chip, as recited in claim 11, further comprising a moldingcompound disposed on said die, on said fillet, on at least one portionof said die attach material, and on at least one portion of said packagebase.
 19. A packaged semiconductor chip, as recited in claim 18, whereinsaid semiconductor chip package base comprises a ball grid array (BGA).20. A packaged semiconductor chip, as recited in claim 11, wherein saidsemiconductor chip package base comprises a ball grid array (BGA).